Mixing Blocking And Non-Blocking Assignments Verilog Examples

I had a hard time over this too.

But firstly, you should understand that non-blocking or blocking is actually nothing to do with whether a latch/ff would be created!

For their difference you could understand it simply(at beginning) by this point: i. If use blocking, sentences after it could not be executed until block sentence LHS assigned value, since what changed to LHS of it could be updated and used if the variable is used. However, for non-blocking, it don't block following sentence like parallel with following sentence(actually RHS calculation should be done first, but it doesn't matter, ignore it when you confuse). The LHS don't change/updated for this time's execution (updated next time when always block trigged again). And following sentence use the old value, as it updated at the end of execution cycle.

One key point is to find whether in you code (always block) there is any case variable not assigned value but could happen. If you don't pass value to it and that case occurs, then latch/ff is created to keep the value.

For example,

Following could also create latch/ff:

--> latch/ffs created for in=1, b no assignment, in=0 a no assignment.

In addition, when you sense posedge of clk , it is bound to end with latch/ff. Because, for clk, there must exist negative edge, and you don't do anything, latch/ffs are created to keep all the old value!

answered Jun 25 '14 at 17:33

I would like to ask three questions about blocking & non-blocking assignment.

The first question is that How the blocking and non-blocking statement works when they are combined.

following the book "FPGA_Prototyping_By_Verilog_Examples" it says that

When an always block is activated, the right-hand-side expressions of nonblocking assignments are evaluated at the beginning of the time step.

Based on the above statement about a non-blocking statement, I've expected that the below always block would require two clocks for assigning value of a&b to the q0, but the book says it can do it in one clock cycle.

At the first glance, I've thought that the value of ab0 (RHS of non-blocking assignment) will be stored in somewhere before the always block is executed and to be used in the q0 <= ab0;. Therefore, I assumed that the value of ab0 will be estimated at the first clock cycle and the estimated value of ab0 will be assigned to the q0 in the second rising edge of the clock.

So my question is, when the value of RHS of non-blocking statements are decided when they are used with the blocking statements. If it is determined regardless of the blocking statement please let me know.

The second questions is How the non-blocking and blocking statements affects the real hardware?

I've read many articles that say the nonblocking and blocking assignments do not have any effect on the synthesis, but only regards to the simulation. If it is just about the simulation, How the hardware really works to executed instructions inside always block? Does it sequentially execute the instructions one by one like the C code?

As far as I know the ground rule is

  • use the non-blocking assignment in the sequential circuit.
  • use the blocking assignment in the cobinational circuit.

However, it seems that using the non-blocking assignment in the combinational circuit and blocking assignment in the sequential circuit are all legitimate and allowed or even mixed!!!

So, my last question is What is the advantage of mixing two assignments or what kind of cases are there to use non-blocking assignment in the combinational circuit and blocking assignment in sequential circuit?

verilog

One thought on “Mixing Blocking And Non-Blocking Assignments Verilog Examples

Leave a Reply

Your email address will not be published. Required fields are marked *